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?2013 silicon storage technology, inc. ds25022b 04/13 data sheet www.microchip.com 1 mbit / 2 mbit / 4 mbit (x8) multi-purpose flash sst39sf010a / sst39s f020a / sst39sf040 features ? organized as 128k x8 / 256k x8 / 512k x8 ? single 4.5-5.5v read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 14 mhz) ? active current: 10 ma (typical) ? standby current: 30 a (typical) ? sector-erase capability ? uniform 4 kbyte sectors ? fast read access time: ? 55 ns ? 70 ns ? latched address and data ? automatic write timing ? internal v pp generation ? fast erase and byte-program ? sector-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 2 seconds (typical) for sst39sf010a 4 seconds (typical) for sst39sf020a 8 seconds (typical) for sst39sf040 ? end-of-write detection ? toggle bit ? data# polling ? ttl i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? 32-pin pdip ? all devices are rohs compliant the sst39sf010a / sst39sf020a / sst39sf040 are cmos multi-purpose flash (mpf) devices manufactured with sst proprietary, high performance cmos superflash technology. the split-g ate cell design and thick oxide tunnel- ing injector attain better reliability and manufacturability comp ared with alternate approaches. the sst39sf010a / sst39sf020a / sst39sf040 write (program or erase) with a 4.5-5.5v power supply , and conforms to jedec standard pinouts for x8 memories
?2013 silicon storage technology, inc. ds25022b 04/13 2 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet product description the sst39sf010a/020a/040 are cmos multi-purpose flash (mpf) manufactured with sst?s propri- etary, high performance cmos superflash technology. the split-gate cell design and thick oxide tun- neling injector attain be tter reliability and manufa cturability compared with al ternate approaches. the sst39sf010a/020a/040 devices write (program or erase) with a 4.5-5.5v power supply. the sst39sf010a/020a/040 devices conform to jedec standard pinouts for x8 memories. featuring high performance byte-program, the sst39sf010a/020a/040 devices provide a maximum byte-program time of 20 sec. these devices use to ggle bit or data# polling to indicate the comple- tion of program operation. to protect against inad vertent write, they have on-chip hardware and soft- ware data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39sf010a/020a/040 devices are suited for applications that require convenient and econom- ical updating of program, configuration, or data memory. for all system applications, they significantly improve performance and reliabilit y, while lowering power consumpt ion. they inherently use less energy during erase and program than alternative fl ash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and pro- gram times increase with accumulated erase/program cycles. to meet high density, surface mount requirements, the sst39sf010a/020a/040 are offered in 32-lead plcc and 32-lead tsop packages. a 600 mil, 32-pin pdip is also available. see figures 2, 3, and 4 for pin assignments.
?2013 silicon storage technology, inc. ds25022b 04/13 3 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet block diagram figure 1: functional block diagram y-decoder i/o buffers and data latches 1147 b1.2 address buffers & latches x-decoder dq 7 - dq 0 memory address oe# ce# we# superflash memory control logic
?2013 silicon storage technology, inc. ds25022b 04/13 4 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet pin assignment figure 2: pin assignments for 32-lead plcc sst39sf010a sst39sf010a sst39sf010a sst39sf010a 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 sst39sf020a sst39sf040 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 sst39sf020a sst39sf040 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 a16 nc v dd we# nc sst39sf020a sst39sf040 a12 a15 a16 nc v dd we# a17 a12 a15 a16 a18 v dd we# a17 32-lead plcc top view 1147 32-plcc p2.4 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 sst39sf020a sst39sf040 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6
?2013 silicon storage technology, inc. ds25022b 04/13 5 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 3: pin assignments for 32-lead tsop (8mm x 14mm) figure 4: pin assignments for 32-pin pdip a11 a9 a8 a13 a14 nc we# v dd nc a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1147 32-tsop p1.1 standard pinout top view die up sst39sf010a a11 a9 a8 a13 a14 a17 we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 sst39sf020a sst39sf040 sst39sf010a oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 sst39sf020a sst39sf040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view 1147 32-pdip p3.2 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss sst39sf010a nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss sst39sf020a a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss sst39sf040 sst39sf010a 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd we# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 sst39sf020a sst39sf040 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3
?2013 silicon storage technology, inc. ds25022b 04/13 6 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet table 1: pin description symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 12 address lines will select the sector. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-stat e when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide 5.0v supply (4.5-5.5v) v ss ground nc no connection unconnected pins. t1.2 25022 1. a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040
?2013 silicon storage technology, inc. ds25022b 04/13 7 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the sst39sf010a/020a/040 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce # is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram (figure 5) for further details. byte-program operation the sst39sf010a/020a/040 are programmed on a byte-by-byte basis. before programming, the sec- tor where the byte exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. during the byte-program operation, the addresses are latched on the fall- ing edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed, within 20 s. see fi gures 6 and 7 for we# and ce# controlled program operation timing diagrams and figure 16 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to per- form additional tasks. any commands written during the internal program operation will be ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector architecture is based on uniform sector size of 4 kbyte. the sector-erase operation is initiated by executing a six-byte command load sequence for software data protection with sector-erase com- mand (30h) and sector address (sa) in the last bus cycle. the sector address is latched on the falling edge of the sixth we# pulse, while the command (30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after th e sixth we# pulse. the end-of-erase can be deter- mined using either data# polling or toggle bit methods. see figure 10 for timing waveforms. any com- mands written during the sector -erase operation will be ignored. chip-erase operation the sst39sf010a/020a/040 provide chip-erase operation, which allows the user to erase the entire memory array to the ?1s? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executin g a six- byte software data protection command sequence with chip-erase command (10h) with address 5555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixt h we# or ce#, whichever occurs first. during the internal erase operation, the only valid read is toggle bit or data# polling. see table 4 for the com- mand sequence, figure 11 for timing diagram, and figure 19 for the flowchart. any commands written during the chip-erase op eration will be ignored.
?2013 silicon storage technology, inc. ds25022b 04/13 8 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet write operation status detection the sst39sf010a/020a/040 provide two software means to detect the completion of a write (pro- gram or erase) cycle, in order to optimize the sys tem write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we# which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read ma y be simultaneous with the comple tion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the wr ite cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the sst39sf010a/020a/040 are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining da ta outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles af ter an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the intern al erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after th e rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip-erase, the dat a# polling is valid after th e rising edge of sixth we# (or ce#) pulse. see figure 8 for data# polling timing diagram and figure 17 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the ne xt operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 9 for toggle bit tim- ing diagram and figure 17 for a flowchart. data protection the sst39sf010a/020a/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 2.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this pre- vents inadvertent writes during power-up or power-down.
?2013 silicon storage technology, inc. ds25022b 04/13 9 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet software data protection (sdp) the sst39sf010a/020a/040 provide the jedec approved software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte load sequence. the sst39sf010a/020a/040 devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode, within t rc. product identification the product identification mode identifies the device as the sst39sf040, sst39sf010a, or sst39sf020a and manufacturer as sst. this mode may be accessed by software operations. users may wish to use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, table 4 for software operation, figure 12 for the software id entry and read timing diagram and figure 18 for the id entry command sequence flowchart. product identificatio n mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exit is accomplished by issuing the exit id command sequence, which returns the device to the read operation. please note that the software reset command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 13 for timing waveform and figure 18 for a flowchart. table 2: product identification address data manufacturer?s id 0000h bfh device id sst39sf010a 0001h b5h sst39sf020a 0001h b6h sst39sf040 0001h b7h t2.2 25022
?2013 silicon storage technology, inc. ds25022b 04/13 10 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet operations table 3: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.3 25022 table 4: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 14 -a 0 (hex), addresses a ms -a 15 can be v il or v ih , but no other value, for the command sequence. a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program 5555h aah 2aaah 55h 5555h a0h ba 2 2. ba = program byte address data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 3 3. sa x for sector-erase; uses a ms -a 12 address lines 30h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 4. the device does not remain in software product id mode if powered down. 5. with a ms -a 1 = 0; sst manufacturer?s id = bfh, is read with a 0 = 0, sst39sf010a device id = b5h, is read with a 0 = 1 sst39sf020a device id = b6h, is read with a 0 = 1 sst39sf040 device id = b7h, is read with a 0 = 1 5555h aah 2aaah 55h 5555h 90h software id exit 6 6. both software id exit operations are equivalent xxh f0h software id exit 6 5555h aah 2aaah 55h 5555h f0h t4.2 25022
?2013 silicon storage technology, inc. ds25022b 04/13 11 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +12 5c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to + 150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hold lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300c surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. table 5: operating range range ambient temp v dd commercial 0c to +70c 4.5-5.5v industrial -40c to +85c 4.5-5.5v t5.1 25022 table 6: ac conditions of test 1 1. see figures 14 and 15 input rise/fall time output load 5ns c l = 30 pf for 55 ns c l = 100 pf for 70 ns t6.1 25022
?2013 silicon storage technology, inc. ds25022b 04/13 12 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet table 7: dc operating characteristics v dd = 4.5-5.5v 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht , at f=1/t rc min v dd =v dd max read 2 25 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 35 ma ce#=we#=v il , oe#=v ih i sb1 standby v dd current (ttl input) 3mace#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 100 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.4 v i ol =2.1 ma, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 a, v dd =v dd min t7.10 25022 1. typical conditions for the active current shown on the front data sheet page are average values at 25c (room temperature), and v dd = 5v for sf devices. not 100% tested. 2. values are for 70 ns conditions. see the multi-purpose flash power rating application note for further information. table 8: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t8.1 25022 table 9: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t9.0 25022 table 10: reliability characteristics symbol parameter minimum sp ecification units test method n end 1,2 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cyc le minimum for the whole device. a se ctor- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t10.2 25022
?2013 silicon storage technology, inc. ds25022b 04/13 13 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet ac characteristics table 11: read cycle timing parameters v dd = 4.5-5.5v symbol parameter sst39sf010a/020a/040-55 sst39sf010a/020a/040-70 units min max min max t rc read cycle time 55 70 ns t ce chip enable access time 55 70 ns t aa address access time 55 70 ns t oe output enable access time 35 35 ns t clz 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 20 25 ns t ohz 1 oe# high to high-z output 20 25 ns t oh 1 output hold from address change 0 0 ns t11.4 25022 table 12: program/erase cycle timing parameters symbol parameter min max units t bp byte-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 40 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t sce chip-erase 100 ms t12.1 25022
?2013 silicon storage technology, inc. ds25022b 04/13 14 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 5: read cycle timing diagram figure 6: we# controlled program cycle timing diagram 1147 f03.1 address a ms-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data va l i d data va l i d t ohz note: a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040 1147 f04.1 address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040
?2013 silicon storage technology, inc. ds25022b 04/13 15 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 7: ce# controlled program cycle timing diagram figure 8: data# polling timing diagram 1147 f05.1 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040 1147 f06.1 address a ms-0 dq 7 dd # d # d we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040
?2013 silicon storage technology, inc. ds25022b 04/13 16 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 9: toggle bit timing diagram figure 10: we# controlled sector-erase timing diagram 1147 f07.1 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note note: toggled bit output is always high first. a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040 1147 f08.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# cont rolled sector-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 10) sa x x = sector address toggled bit output is always high first. a ms = most significant address a ms = a 16 for sst39sf010a, a 17 for sst39sf020a, and a 18 for sst39sf040
?2013 silicon storage technology, inc. ds25022b 04/13 17 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 11: we# controlled chip-erase timing diagram figure 12: software id entry and read 1147 f17.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled sector-era se operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 10) sa x x = sector address toggled bit output is always high first. a ms = most significant address 1147 f09.2 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90 note: device id = b5h for sst39sf010a, b6h for sst39sf020a, and b7h for sst39sf040
?2013 silicon storage technology, inc. ds25022b 04/13 18 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 13: software id exit and reset figure 14: ac input/output reference waveforms figure 15: a test load example 1147 f10.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0 1147 f11.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (3.0v) for a logic ?1? and v ilt (0v) for a logic ?0?. measurement reference points for inputs and outputs are v it (1.5v) and v ot (1.5v). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1147 f12.0 to tester to dut c l r l low r l high v dd
?2013 silicon storage technology, inc. ds25022b 04/13 19 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 16: byte-program algorithm 1147 f13.1 start load data: aah address: 5555h load data: 55h address: 2aaah load data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
?2013 silicon storage technology, inc. ds25022b 04/13 20 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 17: wait options 1147 f14.0 wait t bp , t sce, or t se byte program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte program/erase initiated byte program/erase initiated
?2013 silicon storage technology, inc. ds25022b 04/13 21 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 18: software product command flowcharts 1147 f15.1 load data: aah address: 5555h software product id entry command sequence load data: 55h address: 2aaah load data: 90h address: 5555h wait t ida read software id load data: aah address: 5555h software product id exit & reset command sequence load data: 55h address: 2aaah load data: f0h address: 5555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
?2013 silicon storage technology, inc. ds25022b 04/13 22 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 19: erase command sequence 1147 f16.1 load data: aah address: 5555h chip-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 10h address: 5555h load data: aah address: 5555h wait t sce chip erased to ffh load data: aah address: 5555h sector-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 30h address: sa x load data: aah address: 5555h wait t se sector erased to ffh
?2013 silicon storage technology, inc. ds25022b 04/13 23 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet product ordering information sst 39 sf 010a - 70 - 4c - nhe xx x x xxxx -xx -xx - xxx environmental attribute e 1 = non-pb package modifier h = 32 pins or leads package type n = plcc p = pdip w = tsop (type 1, die up, 8mm x 14mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 55 = 55 ns 70 = 70 ns version a = special feature version device density 040 = 4 mbit 020 = 2 mbit 010 = 1 mbit voltag e s = 4.5-5.5v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devi ces are ?rohs compli- ant?.
?2013 silicon storage technology, inc. ds25022b 04/13 24 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid co mbinations and to determine availability of new combi- nations. valid combinations for sst39sf010a sst39sf010a-55-4c-nhe sst39sf010a-55-4c-whe sst39sf010a-70-4c-nhe sst39sf010a-70-4c-whe sst39sf010a-70-4c-phe sst39sf010a-55-4i-nhe sst39sf010a-55-4i-whe sst39sf010a-70-4i-nhe sst39sf010a-70-4i-whe valid combinations for sst39sf020a sst39sf020a-55-4c-nhe sst39sf020a-55-4c-whe sst39sf020a-70-4c-nhe sst39sf020a-70-4c-whe sst39sf020a-70-4c-phe sst39sf020a-55-4i-nhe sst39sf020a-55-5i-whe sst39sf020a-70-4i-nhe sst39sf020a-70-4i-whe valid combinations for sst39sf040 sst39sf040-55-4c-nhe sst 39sf040-55-4c-whe SST39SF040-70-4C-NHE sst39sf040-70-4c-whe sst39sf040-70-4c-phe sst39sf040-55-4i-nhe sst39sf040-55-4i-whe sst39sf040-70-4i-nhe sst39sf040-70-4i-whe
?2013 silicon storage technology, inc. ds25022b 04/13 25 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet packaging diagrams figure 20: 32-lead plastic lead chip carrier (plcc) sst package code: nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30
?2013 silicon storage technology, inc. ds25022b 04/13 26 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 21: 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0.50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0- 5 detail
?2013 silicon storage technology, inc. ds25022b 04/13 27 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet figure 22: 32-pin plastic dual in-line pins (pdip) sst package code: ph 32-pdip-ph-3 pin #1 identifier c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .200 .170 7 4 plcs. .600 bsc .100 bsc .150 .120 .022 .016 .065 .045 .080 .070 .050 .015 .075 .065 1.655 1.645 .012 .008 0 15 .625 .600 .550 .530
?2013 silicon storage technology, inc. ds25022b 04/13 28 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39sf010a / sst39sf020a / sst39sf040 data sheet table 13: revision history revision description date 02 ? 2002 data book may 2002 03 ? changes to table 7 on page 12 ? added footnote for mpf power usage and typical conditions ? clarified the test conditions for power supply current and read parameters ? clarified i dd write to be program and erase mar 2003 04 ? document status changed from ?preliminary specification? to ?data sheet? ? changed i dd program and erase max values from 25 to 35 in table 7 on page 12 oct 2003 05 ? 2004 data book ? added non-pb mpns and removed footnote (see page 24) nov 2003 06 ? corrected revision history for version 04: i dd max value was incorrectly stated as 30 ma instead of 35 ma aug 2004 07 ? removed leaded parts from valid combinations. see psn-d0pb0001 mar 2009 08 ? changed endurance from 10,000 to 100,000 in product description, page 1 sep 2009 09 ? end of life for all 45 ns valid combinations. see s71147(02). ? added replacement 55 ns valid combinations jan 2010 a ? all 45 ns parts reinstated. ? applied new document format ? released document under letter revision system ? updated spec number from s71147 to ds25022 jul 2011 b ? end of life for all 45 ns valid combinations. ? updated table 6 and table 11 apr 2013 ? 2013 silicon storage technology, inc?a microchi p technology company. all rights reserved. sst, silicon storage technology, the sst l ogo, superflash, mtp, and flashflex are regi stered trademarks of silicon storage tech - nology, inc. mpf, sqi, serial quad i/o, and z-scale are trad emarks of silicon storage technology, inc. all other trademarks and registered trademarks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for th e most recent documentation. for the most current package drawings, please see the packaging specific ation located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity ; actual usable capacity may be less. sst makes no warranty for the use of its products other than those ex pressly contained in the standar d terms and conditions of sale. for sales office locations and information, please see www.microchip.com. silicon storage technology, inc. a microchip technology company www.microchip.com isbn:978-1-62077-167-9

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